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Students of computer processor architectures will find the following diagram familiar.
(Click to enlarge)
Figure 1. 7 stage pipelined RISC processor functional block diagram.
This is a functional block diagram of a generic seven-stage pipelined RISC processor. The design achieves maximum performance when the signal propagation delay through each pipeline stage is equal. An imbalance in propagation delay between stages means that one stage requires a slower clock rate than all others. In practice there is only clock for the entire pipeline, so the slow clock requirement of the imbalanced stage slows down the entire design. To speed up this imbalanced stage, the designer should move some of its logic to neighboring pipeline stages.
Students of video processor architectures will find the following diagram familiar.
(Click to enlarge)
Figure 2. Digital video player functional block diagram.
This is a functional block diagram of a generic digital video player. Such devices typically consist of a combination of programmable processor cores and fixed-function Verilog HDL modules. Unlike a traditional RISC processor, each functional block of a digital video player exchanges data with its neighbors through unidirectional FIFOs. FIFOs allow for data dependent processing time at different stages in the pipeline as long as the average throughput of each stage is balanced. The point here is that video pipelines are conceptually similar to traditional processer pipelines. As in a RISC processor, a key goal for the video pipeline designer is to balance the stages.
A key question for the video pipeline designer is where to use processor IP and where to use Verilog HDL modules. Verilog HDL modules are typically designed to use silicon area and energy as efficiently as possible. Fixed function Verilog HDL modules also offer the benefit of deterministic data processing time, which minimizes the size of FIFO memories required. The downside of fixed-function modules is that they are inflexible and may not be able to accommodate different video standards and changing product requirements. Thus there has been a rising interest in programmable processor cores for video processing pipelines.
Performing the required functions is impossible with most traditional programmable processor IP cores because their SIMD parallelism is not scalable to arbitrarily wide data paths. Wide data paths are necessary to handle the required throughput rates. The maximum data throughput rates for real-time operation of typical full HD video playing devices are shown in the following table.
Table 1. Sample data rates.[1]
In contrast to the traditional approach, practically limitless SIMD scalability is offered today by two processor IP core vendors: Tensilica[2] and Silicon Hive. These vendors' cores allow the video processing pipeline designer to configure processors with data paths as wide as necessary to meet throughput requirements. Furthermore, Tensilica and Silicon Hive's processors approach the efficiency of Verilog HDL modules by allowing the definition of arbitrary data type sizes. Most other processors, with data paths tied to power-of-two multiples of bytes, would wastefully require 16-bit data paths to handle 10-bit per pixel video data (for example).
Tensilica and Silicon Hive each have their advantages. Silicon Hive supports wide VLIW instructions, which allows its processors to be easily programmed with complex combinations of operations in each cycle. In contrast, Tensilica has a 64-bit maximum instruction length. This leads to a small area advantage due to smaller code size, but it makes the processors more challenging to program. (In order to fully use Tensilica's hardware, designers must implement complex state machines in custom processor state registers.)
Whichever vendor most seriously devotes its development resources to video stands to win a strong position as the processor provider of choice for future video display processing pipelines. Of course, there is always the possibility of new vendors entering the market with a competitive offering. It will be interesting to see how this market evolves.
About the author
Jonah Probell is a microprocessor architect and digital video expert. He runs the Web site VideoBits.ORG.
Footnotes
[1] As defined by the Blu-ray disc standard.
[2] The author was formerly employed by Tensilica.
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